Vias are one of the key components of multilayer PCBs, and the cost of drilling typically accounts for 30% to 40% of the total PCB manufacturing cost.
Simply put, every hole on a PCB can be referred to as a via.
Basic Concepts of Vias
In terms of function, vias can be divided into two categories: those used for electrical connections between layers, and those used for securing or positioning components.
From a manufacturing process perspective, these vias are generally classified into three types: blind vias, buried vias, and through-holes.
Blind vias are located on the top and bottom surfaces of the printed circuit board (PCB) and have a certain depth.
They are used to connect surface-level circuits with underlying internal layers, and the depth of the via typically does not exceed a certain ratio (of the via diameter).
Buried vias refer to connection holes located within the inner layers of a printed circuit board; they do not extend to the board’s surface.
Both of the aforementioned types of vias are located within the inner layers of the board and are created using the through-hole forming process prior to lamination; during the via formation process, multiple inner layers may be stacked.
The third type is called a through-hole, which penetrates the entire PCB and can be used for internal interconnections or as mounting and positioning holes for components.
Since through-holes are easier to manufacture and have lower costs, the vast majority of printed circuit boards use them rather than the other two types of vias.
Unless otherwise specified, all vias mentioned below are considered through-holes.
Via Structure and Design Considerations
From a design perspective, a via consists primarily of two parts: the central drill hole and the pad area surrounding it.
The dimensions of these two parts determine the size of the via.
Obviously, when designing high-speed, high-density PCBs, designers always prefer vias to be as small as possible, as this leaves more space on the board for routing.
Furthermore, the smaller the via, the lower its parasitic capacitance, making it more suitable for high-speed circuits.
However, reducing hole size also increases costs, and the size of vias cannot be reduced indefinitely; it is constrained by manufacturing processes such as drilling and plating: the smaller the hole, the longer the drilling time required, and the more likely it is to deviate from the center position; furthermore, when the hole depth exceeds six times the drill diameter, uniform copper plating on the hole walls cannot be guaranteed.
Microvias and Advanced Manufacturing Limits
For example, if a standard 6-layer PCB has a thickness (via depth) of 50 mils, under normal conditions, the smallest drill diameter a PCB manufacturer can provide is typically 8 mils.
With the development of laser drilling technology, drill sizes can become increasingly smaller; generally, vias with a diameter of 6 mils or less are referred to as microvias.
Microvias are frequently used in HDI (High-Density Interconnect) designs.
Microvia technology allows vias to be drilled directly onto pads, which significantly improves circuit performance and saves routing space.
Electrical Effects of Vias in High-Speed Circuits
Vias act as discontinuities in the impedance of transmission lines, causing signal reflections.
Generally, the equivalent impedance of a via is about 12% lower than that of a transmission line.
For example, a 50-ohm transmission line will experience a 6-ohm reduction in impedance when passing through a via (the exact reduction depends on the via size and board thickness and is not absolute).
However, the reflections caused by impedance discontinuities at vias are actually negligible, with a reflection coefficient of only:
(44-50)/(44+50)=0.06
The issues associated with vias are primarily related to the effects of parasitic capacitance and inductance.
Parasitic Capacitance and Inductance of Via Holes
Via holes inherently exhibit parasitic stray capacitance.
If the diameter of the solder mask opening on the ground plane is known to be D2, the diameter of the via pad is D1, the PCB thickness is T, and the dielectric constant of the board substrate is ε, then the parasitic capacitance of the via hole can be approximated as:
C = 1.41εTD1/(D2 – D1).
The primary effect of a via’s parasitic capacitance on a circuit is to prolong the signal rise time, thereby reducing the circuit’s speed.
Numerical Example of Parasitic Capacitance and Rise Time Impact
For example, for a PCB with a thickness of 50 mils, if the via pad diameter is 20 mils (drill diameter is 10 mils) and the solder mask diameter is 40 mils, we can use the above formula to approximate the via’s parasitic capacitance as:
C = 1.41 × 4.4 × 0.050 × 0.020 / (0.040 – 0.020) = 0.31 pF
The change in rise time caused by this capacitance is approximately:
T10–90 = 2.2C(Z0/2) = 2.2 × 0.31 × (50/2) = 17.05 ps
These values show that while the rise time delay caused by the parasitic capacitance of a single via is not very significant, if multiple vias are used for interlayer transitions in a trace, the cumulative effect becomes substantial and must be carefully considered during design.
In actual design, parasitic capacitance can be reduced by increasing the distance between the via and the copper pad (Anti-pad) or by reducing the diameter of the pad.
Parasitic Inductance and Its Dominant Impact in High-Speed Circuits
Vias exhibit both parasitic capacitance and parasitic inductance.
In the design of high-speed digital circuits, the adverse effects of a via’s parasitic inductance often outweigh those of its parasitic capacitance.
Its parasitic series inductance reduces the contribution of bypass capacitors, thereby diminishing the filtering effectiveness of the entire power supply system.
Empirical Calculation of Via Parasitic Inductance
We can use the following empirical formula to roughly calculate the approximate parasitic inductance of a via:
L = 5.08h[ln(4h/d) + 1]
where L is the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole.
As can be seen from the equation, the diameter of the via has a relatively small effect on the inductance, while the length of the via has the greatest influence.
Using the example above, the inductance of the via can be calculated as:
L = 5.08 × 0.050 [ln(4 × 0.050 / 0.010) + 1] = 1.015 nH
- High-Frequency Impedance Effect and Design Considerations
If the signal rise time is 1 ns, then its equivalent impedance is:
XL = πL / 10⁻¹⁰ = 3.19 Ω.
Such impedance cannot be ignored when high-frequency currents are flowing.
It is particularly important to note that when a bypass capacitor connects the power plane to the ground plane, it must pass through two vias, which will cause the parasitic inductance of the vias to increase exponentially.
How to Use Via Holes
Based on the analysis of via parasitic characteristics above, we can see that in high-speed PCB design, via holes—which may seem simple—can often have significant negative effects on circuit design.
To minimize the adverse effects of via parasitic effects, the following practices should be followed in the design process:
1. Select a reasonable via size based on both cost and signal quality.
If necessary, consider using different via sizes; for example, larger vias can be used for power or ground lines to reduce impedance, while smaller vias can be used for signal traces.
Of course, as the via size decreases, the corresponding cost will increase.
2. From the two formulas discussed above, it can be concluded that using thinner PCB boards helps reduce both parasitic parameters of vias.
3. Signal traces on the PCB should avoid changing layers whenever possible; in other words, avoid using unnecessary vias.
4. Power and ground pins should have vias placed as close as possible; the shorter the trace between the via and the pin, the better.
Consider placing multiple vias in parallel to reduce equivalent inductance.
5. Place ground vias near signal vias where signal paths change layers to provide the nearest return path for the signal.
You may even place some extra ground vias on the PCB.
6. For high-density, high-speed PCBs, consider using microvias.
Conclusion
Vias play a critical structural and electrical role in multilayer PCB design, but their impact extends far beyond simple interlayer connectivity.
As demonstrated, their parasitic capacitance and inductance introduce measurable effects on signal integrity, including rise-time delay, impedance discontinuities, and high-frequency power distribution degradation.
Although the impact of a single via may appear negligible, cumulative effects in high-speed, high-density interconnect (HDI) designs can significantly compromise circuit performance.
From a design and manufacturing perspective, via geometry, PCB thickness, and fabrication constraints are tightly coupled, requiring a balanced trade-off between cost, manufacturability, and electrical performance.
Advanced techniques such as microvias, optimized anti-pad design, and controlled via sizing provide effective pathways to mitigate these issues.
Ultimately, successful high-speed PCB design depends on minimizing unnecessary via transitions, optimizing layer-change strategies, and carefully managing return paths and power integrity.
By applying structured design rules and understanding via parasitics at both theoretical and practical levels, engineers can significantly improve signal integrity, reduce losses, and ensure reliable operation in modern high-performance electronic systems.
