This study focuses on finished chips that have already been packaged. Since there is no accurate model of their internal structure, the analysis primarily relies on external geometry and the layout of solder joints.
Information regarding internal structures, such as the internal structure of the wafer and certain material properties, cannot be determined.
Therefore, to balance accuracy and practicality while ensuring the validity of the simulation, the following two strategies are employed:
Structural Simplification Strategy:
The substrate and wafer are treated as homogeneous materials; internal multilayer wiring is disregarded, and only the macroscopic outline is retained.
Bonding pads are initially simplified to a solid plane, which is later replaced by the bonding pads and fill layers from the complete model.
Material Parameter Calibration Method:
By comparing warpage measurements with actual Shadow Moire test results, material parameters are adjusted within a certain range to obtain parameters suitable for subsequent simulations.
Overall Simulation Workflow
Phase 1: Material Parameter Calibration and Structural Simplification
The focus of the first phase is to establish an equivalent material parameter system for subsequent loading by comparing results from structural simplification with thermal deformation experiments.
Given the inability to obtain specific models of the multi-layer substrate, chip stack, and materials inside the package, the chip model is structurally simplified to a homogeneous body.
The initial temperature state is set to match the neutral stress temperature in the shadow pattern experiments to avoid the influence of missing internal residual stresses on deformation trends.
Subsequently, by simulating the heating process and comparing warpage magnitude and trends with the shadow pattern test results, adjustments are made within the range of material parameters to ensure the model exhibits a reasonable thermal response under the input conditions.
Phase 2: Reflow Soldering Thermal-Structural Simulation with Cyclic Loading
The second stage involves modeling and loading simulations for the entire reflow soldering process.
Using the provided reflow soldering temperature curve, four, five, and six loading cycles are performed, respectively.
After each set of reflow soldering loads, temperature cycling conditions are sequentially applied for fatigue analysis.
Transient thermal analysis is coupled with transient structural analysis to enable the model to exhibit the progressive changes in structural deformation and stress fields under multiple thermal cycles.
The results from this stage will serve as the load basis for subsequent local analyses and also provide deformation data for the overall structure under thermal loading conditions.
Phase 3: Solder Joint Fatigue Analysis Using Submodeling and Darveaux Theory
The third stage involves solder joint fatigue analysis.
Based on the problem and structural response results from the second stage, strain distribution results are used to quickly identify regions of energy concentration; submodels with realistic geometric details are then constructed for these identified regions, incorporating local mesh refinement and material properties, and the corresponding temperature and deformation loads are applied.
Based on this, Darveaux theory is applied to calculate the equivalent plastic strain of the solder joints and related fatigue indices, thereby evaluating the potential extent of damage accumulation during multiple thermal cycles.
Material Benchmarking and Simulation
Model Simplification and Thermal Loading Settings
The primary objective of this phase is to obtain material parameter inputs for subsequent reflow soldering simulations.
Regarding modeling, since the project subject is a finished, packaged chip, a structural simplification strategy is adopted: key areas such as the chip and substrate are treated as homogeneous bodies, retaining only the macroscopic geometric structure and interlayer relationships without incorporating specific wiring structures or multilayer stacks.
The solder joints between the chip and substrate are simplified to uniform thin plates.
Based on actual reflow soldering test reports, it is recognized that the chip possesses initial residual stress at room temperature (25°C).
According to the chip’s oven temperature profile, 150°C is identified as the neutral stress point.
Therefore, in the simulation’s initial conditions, the overall initial temperature of the chip is set to 150°C.
The process then involves cooling to 25°C, followed by heating to 237°C, and finally cooling back to 25°C.
This process uses transient thermal analysis to obtain the temperature field distribution and then imports it into transient structural analysis to calculate the deformation response of the chip during the thermal loading process.
The model boundary conditions include the configuration of the chip model as a 1/4 symmetry to improve computational efficiency.
At the center of the complete chip model—specifically, at the intersection of the two symmetrical surfaces of the 1/4 model—the process applies a remote displacement along the thickness direction and constrains all degrees of freedom for displacement and rotation in all directions.
The process applies elastic support constraints to the surface of the chip’s heat sink ring, using a numerical value equivalent to the chip’s own density.
The process takes this step to achieve better convergence in the 1/4 symmetric model.
Material Parameter Fitting and Bayesian Optimization Strategies
Due to limitations in material data and modeling, a set of material parameters suitable for simulation must be fitted by comparing experimental data.
This paper employs a reverse fitting method with warpage response as the objective: typical initial ranges for the coefficient of thermal expansion (CTE), Young’s modulus, and Poisson’s ratio from the material library.
The simulation outputs structural deformation, and the process compares it with actual data collected before and after a single reflow soldering cycle.
During this process, ANSYS response surface analysis screens parameters with higher fit near the approximate results, and the process gradually adjusts the input parameters to bring the trend of simulated deformation as close as possible to the measured data.
To improve the efficiency of parameter search, this project introduced a Bayesian optimization algorithm implemented in Python.
This method uses structural warpage error as the evaluation function to automatically screen for and predict the optimal parameter combination through multiple rounds of simulation trials.
When exploring the parameter space, Bayesian optimization effectively integrates historical information with prediction uncertainty, thereby accelerating convergence and reducing unnecessary repetitive simulations in scenarios with a limited number of parameters.
Comparison of Material Parameters and Warpage Results
The final set of material parameters includes the CTE, elastic modulus, and density values for each material.
After performing thermal loading simulations using this set of parameters, the Y-displacement curve of the bottom diagonal of the chip substrate was extracted and compared with the warpage trends measured in the shadow pattern experiments.
This confirmed that the warpage trends obtained from this set of material parameters matched the experimental results, with upward warpage occurring at the center and four corners, and a concave depression in the inner ring.
The maximum deformation before the first reflow was 1.328E-04 m, or 132.8 microns.
The maximum deformation after the first reflow was 1.547E-04 m, or 154.7 microns.
The difference between the two was 21.9 microns.
The results met the requirements of 130 ± 10 microns before the first reflow, 155 ± 10 microns after the first reflow, and a difference of 25 ± 5 microns.
The comparison results show that the overall warpage trend of the simulation model before and after reflow soldering exhibits good consistency with the experimental data, and the location of maximum deformation and the magnitude of deformation are close to the range observed in the experiments.
This set of parameters can be used for subsequent multi-cycle thermal analysis, providing a solid foundation for deformation prediction and local fatigue analysis during the reflow soldering process.
Reflow Soldering Simulation
Initial Temperature and Boundary Conditions
After fitting the material parameters, the process accounts for the clamping method used in the actual soldering process, where the bottom surface of the substrate remains free.
Using the same modeling structure, the process conducts a thermal-structural analysis of six reflow soldering cycles.
The objective of this simulation phase was to evaluate the accumulation of deformation and trends in stress changes in the chip structure following multiple cycles of typical reflow soldering temperature excursions.
The simulation utilizes a provided typical reflow soldering temperature profile, which includes multiple stages such as heating, isothermal holding, and cooling, and reflects the temperature fluctuation characteristics of the actual process at different time points.
Given the initial modeling temperature of 150°C, the process performs a transient thermal step to reduce the model temperature from 150°C to the reflow soldering start temperature of 25°C before applying the reflow soldering profile, in order to simulate the actual physical pathway.
Subsequently, the process applies the six-cycle reflow soldering process in a single run.
The process applies the complete single-cycle reflow soldering temperature profile sequentially six times to obtain specific temperature variation data.
The process then imports the temperature distribution into the transient structural analysis module to obtain the thermal stress and deformation response of the structure under the six-cycle reflow soldering conditions.
Six-Cycle Loading Simulation Setup
The six-cycle reflow soldering process simulation employs sequential loading.
The process uses a 900-second interval from the start of heating to the end of the temperature rise, as shown in the reflow soldering temperature curve, and takes data points every 50 seconds.
The process repeats this cycle six times, resulting in a total loading duration of 5,400 seconds.
This method effectively reflects the trends in residual deformation and stress evolution caused by multiple thermal cycles within the chip.
The loading process also includes a TC temperature cycle for subsequent fatigue analysis: cooling from room temperature to -40°C, holding at low temperature for 900 seconds, heating to 125°C, holding at high temperature for 900 seconds, and cooling back to room temperature, with a temperature change rate of 5°C per minute.
This temperature cycle curve is used exclusively for fatigue analysis following the six reflow soldering cycles.
During the loading process, the structural model uses the same boundary conditions as those defined for the material.
The simulation establishes frictionless contact between the chip and the simulation platform, applies fixed constraints around the platform’s perimeter, and applies global gravitational acceleration in the -Y direction.
The analysis uses the maximum structural deformation, maximum principal stress, and maximum equivalent strain values from each thermal cycle for subsequent analysis when importing the solder joint sub-model.
Presentation of Reflow Soldering Simulation Results
After completing each round of reflow soldering simulations, the following key response data were extracted from the overall model; see Table 1 for details.
Diagonal deformation curves of the PCB after each reflow soldering cycle;
Maximum, minimum, and difference in substrate deformation after each reflow process.
Note: Since a 1/4 model is used, all warpage curves show only the left half of the diagonal warpage.
The cumulative trend of structural deformation after six thermal cycles shows that residual warpage deformation appears in the overall chip following multiple temperature rise and fall cycles.
| Reflow Cycle | Max Warpage (+) (m) | Max Warpage (−) (m) | Difference (m) | Difference (μm) |
|---|---|---|---|---|
| 1st Reflow | 1.1615E-04 | -3.8925E-05 | 1.5508E-04 | 155.075 |
| 2nd Reflow | 1.1612E-04 | -1.6358E-05 | 1.3248E-04 | 132.478 |
| 3rd Reflow | 9.1384E-05 | -1.9916E-04 | 2.9054E-04 | 290.544 |
| 4th Reflow | 9.1613E-05 | -1.7554E-04 | 2.6715E-04 | 267.153 |
| 5th Reflow | 1.3702E-04 | -2.0211E-04 | 3.3913E-04 | 339.13 |
| 6th Reflow | 8.2163E-05 | -1.0723E-04 | 1.8939E-04 | 189.393 |
Table 1. Warpage After Each of Six Reflow Soldering Cycles
Solder Joint Fatigue Analysis
Submodel Extraction and Refinement Strategy
To evaluate the fatigue damage that may occur in the solder joints between the die and the substrate inside the chip after multiple reflow cycles, submodel analysis is employed in this phase.
Based on regions of concentrated strain energy response identified from the strain map of the full model, the submodel constructs a solder joint–filler layer combination model with realistic geometry, refines the local mesh, and performs fatigue analysis on critical solder joints.
The models used in the submodels are based on solder joints and fill layers derived from microscopic images of the solder joints.
The modeling represents one quarter of the complete solder joint layer.
In practice, engineers determine specific regions based on the strain cloud map from the full model and utilize only the relevant local sections.
Submodel Import and Fatigue Analysis
During submodel creation, the process extracts the temperature field and boundary displacements of the weld region from the full simulation model and imports them into the local model as thermal-structural boundary conditions.
After importing the temperature field and boundary displacements, the process first identifies regions of strain concentration in the full submodel using contour plots of equivalent variables to select the submodel region, as shown in Figure 1.
After determining the approximate region, the process refines the area within that region in intervals of 100 to 200 weld points until it identifies the weld point with the highest energy density, and then extracts its energy density, as shown in Figure 2.
Once the process determines the location with the maximum energy density in the entire weld layer, it applies the Darveaux theory using the weld point energy density to calculate the weld point life under loading temperature cycles after four, five, and six reflow soldering cycles, respectively.
Fatigue Analysis Results
Based on the results of the Darveaux theory fatigue analysis of solder joints using a 1/4-scale model, the location with the highest energy density within the solder joint layer is expected to be near the center of the intact wafer.
Based on an analysis of the maximum value for a single solder joint, Darveaux theory calculations indicate that after four reflow soldering cycles, a crack will form at this location after 9.40514717811e+25 temperature cycles, followed by joint failure after an additional 4.83750914167e+17 temperature cycles;
After five reflow soldering cycles, the joint at this location will develop cracks after 1.97323846332e+23 temperature cycles, and then fail after an additional 9.07604413759e+16 temperature cycles;
After six reflow soldering cycles, the solder joint at this location will develop cracks after 2.63322627458e+21 temperature cycles, and then fail after an additional 5.61324490613e+14 temperature cycles.
Conclusion
Analysis of the temperature cycles during the fourth, fifth, and sixth reflow soldering processes, together with the fatigue test results from each group, shows that each additional reflow soldering cycle reduces the number of cycles until crack initiation in temperature-cycle fatigue tests by approximately two orders of magnitude.
It also reduces the number of cycles from crack initiation to joint failure by one to two orders of magnitude.
This thermal fatigue simulation study of the SMT process provides guidance for practical engineering applications, helping to prevent products with reliability risks from reaching customers.
